industrial temperature range idt74lvch16702a 3.3v cmos 18-bit read/write buffer with 5v tolerant i/o 1 october 1999 industrial temperature range the idt logo is a registered trademark of integrated device technology, inc. ? 1999 integrated device technology, inc. dsc-4234/1 features: ? typical t sk(o) (output skew) < 250ps ? esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) ?v cc = 3.3v 0.3v, normal range ?v cc = 2.7v to 3.6v, extended range ? cmos power levels (0.4 w typ. static) ? all inputs, outputs, and i/o are 5v tolerant ? supports hot insertion ? available in ssop, tssop, and tvsop packages functional block diagram drive features: ? high output drivers: 24ma ? reduced system switching noise applications: ? 5v and 3.3v mixed voltage systems ? data communication and telecommunication systems idt74lvch16702a 3.3v cmos 18-bit read/write buffer with 5 volt tolerant i/o description: the lvch16702a 18-bit read/write buffer is built using advanced dual metal cmos technology. the device is designed as an 18-bit read/write buffer with a four deep fifo and a read-back latch. it can be used as a read/ write buffer between a cpu and a memory or to interface a high-speed bus and a slow peripheral. the a-to-b (write) path has a four deep fifo for pipelined operations. the fifo can be reset and a fifo full condition is indicated by the full flag ( ff ). the b-to-a (read) path has a latch. all pins can be driven from either 3.3v or 5v devices. this feature allows the use of this device as a translator in a mixed 3.3v/5v supply system. the lvch16702a has been designed with a 24ma output driver. this driver is capable of driving a moderate to heavy load while maintaining speed performance. the lvch16702a has ?bus-hold? which retains the inputs? last state whenever the input goes to a high impedance. this prevents floating inputs and eliminates the need for pull-up/down resistors. b 1:18 ff clk reset oeab wce rce fifo (4 deep) 18 oeba register a 1:18 18 ce d q ce 28 55 29 2 56 30 1 27
industrial temperature range 2 idt74lvch16702a 3.3v cmos 18-bit read/write buffer with 5v tolerant i/o ssop/ tssop/ tvsop top view pin configuration symbol description max unit v term terminal voltage with respect to gnd ?0.5 to +6.5 v t stg storage temperature ?65 to +150 c i out dc output current ?50 to +50 ma i ik continuous clamp current, ?50 ma i ok v i < 0 or v o < 0 i cc continuous current through each 100 ma i ss v cc or gnd absolute maximum ratings (1) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. note: 1. as applicable to the device type. symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 4.5 6 pf c out output capacitance v out = 0v 6.5 8 pf c i/o i/o port capacitance v in = 0v 6.5 8 pf capacitance (t a = +25c, f = 1.0mhz) oeab gnd v cc a 4 gnd gnd v cc a 15 ce 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 48 49 50 51 52 53 54 55 56 1 gnd v cc gnd gnd v cc gnd gnd 25 26 27 28 32 31 30 29 reset wce a 1 a 2 a 3 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 16 a 17 a 18 oeba rce clk b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 10 b 11 b 12 b 9 b 13 b 14 b 15 b 16 b 17 b 18 ff
industrial temperature range idt74lvch16702a 3.3v cmos 18-bit read/write buffer with 5v tolerant i/o 3 note: 1. these pins have "bus-hold". all other pins are standard inputs, outputs, or i/os. pin names i/o description a 1-18 i/o 18 bit i/o port. b 1-18 i/o 18 bit i/o port. clk i clock input. wce i enable pin for fifo input clock. when wce is low data clocks into the fifo on the rising edge of clk. rce i enable pin for fifo output clock. when rce is low data clocks out of the fifo on the rising edge of clk. ff o write path fifo full flag. goes low when fifo is full. when fifo is full all further writes to the fifo are inhibited. when fifo is empty all reads from the fifo are inhibited. reset i synchronous fifo reset - when low clk resets the fifo. the fifo pointers are initialized to the ?empty? condition and fifo ou tput is forced high (all ones). the fifo full flag ( ff ) will be high immediately after reset. oeab i output enable pin for b port. oeba i output enable pin for a port. ce i clock enable pin for b to a register. pin description function table (1) inputs outputs oeba oeab ce clk ax bx notes lhl b to a b bus activity lhh q (2) (a) b bus activity hhl q (2) (a)bus hold hlx a to b signal is dela yed by 4 cloc ks see timing diagram lll q (2) (a) - 5 clocks case not recommended llh q (2) (b) q (2) (a) - 5 clocks case not recommended hhh q (2) (a)bus hold q (2) (b) bus hold notes: 1. h = high voltage level l = low voltage level x = don?t care = low-to-high transition 2. level of q before the indicated steady-state input conditions were established. functional description this device is useful as a read/write buffer for modular high end designs. it provides multi-level buffering in the write path and single deep buffering in the read path, and is suited to write back cache implementation. the read path provides a register for full synchronous operation. the four deep fifo uses one clock with two clock enable pins, wce and rce to clock data in and out. the fifo has an external full flag which goes low when the fifo is full. internal read and write pointers keep track of the words stored in the fifo. a write attempt to a full fifo is ignored. an attempt to read from an empty fifo will have no effect and the last read data remains at the output of the fifo. the fifo may be reset by the synchronous reset input. this resets the read and write pointers to the original ?empty? condition and also sets all b outputs = 1. simultaneous read and write attempts (clock data into fifo as well as clock data out of fifo) are possible except on fifo empty and full boundaries. when the fifo is empty, and a simultaneous read and write is attempted, the read is ignored while the write is executed. if the same is attempted when the fifo is full, the write is ignored while the read is executed. normal operation of the four deep fifo in the write path is independent of the read path operation.
industrial temperature range 4 idt74lvch16702a 3.3v cmos 18-bit read/write buffer with 5v tolerant i/o symbol parameter test conditions min. typ. (1) max. unit v ih input high voltage level v cc = 2.3v to 2.7v 1.7 ? ? v v cc = 2.7v to 3.6v 2 ? ? v il input low voltage level v cc = 2.3v to 2.7v ? ? 0.7 v v cc = 2.7v to 3.6v ? ? 0.8 i ih input leakage current v cc = 3.6v v i = 0 to 5.5v ? ? 5a i il i ozh high impedance output current v cc = 3.6v v o = 0 to 5.5v ? ? 10 a i ozl (3-state output pins) i off input/output power off leakage v cc = 0v, v in or v o 5.5v ? ? 50 a v ik clamp diode voltage v cc = 2.3v, i in = ?18ma ? ?0.7 ?1.2 v v h input hysteresis v cc = 3.3v ? 100 ? mv i ccl quiescent power supply current v cc = 3.6v v in = gnd or v cc ?? 10a i cch i ccz 3.6 v in 5.5v (2) ?? 10 ? i cc quiescent power supply current one input at v cc - 0.6v, other inputs at v cc or gnd ? ? 500 a variation dc electrical characteristics over operating range following conditions apply unless otherwise specified: operating condition: t a = ?40c to +85c notes: 1. typical values are at v cc = 3.3v, +25c ambient. 2. this applies in the disabled state only. timing diagram clk reset wce oeab a [1:18] ff b [1:18] rce word 1 word 2 word 3 word 4 word 1 word 2 word 3 word 4 write cycles cycle 1 cycle 2 cycle 3 cycle 4 cycle 1 cycle 2 cycle 3 cycle 4 read cycles
industrial temperature range idt74lvch16702a 3.3v cmos 18-bit read/write buffer with 5v tolerant i/o 5 note: 1. v ih and v il must be within the min. or max. range shown in the dc electrical characteristics over operating range table for the appropriat e v cc range. t a = ? 40c to + 85c. output drive characteristics symbol parameter test conditions (1) min. max. unit v oh output high voltage v cc = 2.3v to 3.6v i oh = ? 0.1ma v cc ? 0.2 ? v v cc = 2.3v i oh = ? 6ma 2 ? v cc = 2.3v i oh = ? 12ma 1.7 ? v cc = 2.7v 2.2 ? v cc = 3v 2.4 ? v cc = 3v i oh = ? 24ma 2 ? v ol output low voltage v cc = 2.3v to 3.6v i ol = 0.1ma ? 0.2 v v cc = 2.3v i ol = 6ma ? 0.4 i ol = 12ma ? 0.7 v cc = 2.7v i ol = 12ma ? 0.4 v cc = 3v i ol = 24ma ? 0.55 operating characteristics, v cc = 3.3v 0.3v, t a = 25c symbol parameter test conditions typical unit c pd power dissipation wce mode, oeab = 0 c l = 0pf, f = 10mhz pf c pd power dissipation rce mode, oeba = 0 c pd registered channel (b to a) power dissipation oeba = 0; ce = 0 c pd registered channel power dissipation oeba = 0; ce = 1 bus-hold characteristics symbol parameter (1) test conditions min. typ. (2) max. unit i bhh bus-hold input sustain current v cc = 3v v i = 2v ? 75 ? ? a i bhl v i = 0.8v 75 ? ? i bhh bus-hold input sustain current v cc = 2.3v v i = 1.7v ? ? ? a i bhl v i = 0.7v ? ? ? i bhho bus-hold input overdrive current v cc = 3.6v v i = 0 to 3.6v ? ? 500 a i bhlo notes: 1. pins with bus-hold are identified in the pin description. 2. typical values are at v cc = 3.3v, +25c ambient.
industrial temperature range 6 idt74lvch16702a 3.3v cmos 18-bit read/write buffer with 5v tolerant i/o switching characteristics (1) v cc = 2.7v v cc = 3.3v 0.3v symbol parameter test conditions min. max. min. max. unit propagation delays 1 clk to a 1-18 read path/register ? 7.5 ? 6.5 ns 2 clk to ff write path ? 8.2 ? 7.2 ns 3 clk to b 1-18 write path ? 7.5 ? 6.5 ns 4 output skew (2) write path ? ? ? 1 ns setup & hold times 5a 1-18, b1-18 to clk (low to high) setup write path 2.1 ? 1.8 ? ns 6a 1-18, b1-18 to clk (low to high) hold write path 1.3 ? 1 ? ns 7 ce (low) to clk setup read path/register 2.4 ? 2.1 ? ns 8 ce (low) to clk hold read path/register 1.3 ? 1 ? ns 9 wce , rce (low) to clk setup write path 3.8 ? 3 ? ns 10 wce , rce (low) to clk hold write path 1 ? 0.7 ? ns 11 reset (low) to clk setup write path 2.1 ? 1.8 ? ns 12 reset (low) to clk hold write path 1.3 ? 1 ? ns enable & disable times 13 oeba low to a 1-18 enable write path ? 7 ? 6 ns 14 oeba high to a 1-18 disable write path ? 7 ? 6 ns 15 oeab low to b 1-18 enable read path ? 7 ? 6 ns 16 oeab high to b 1-18 disable read path ? 7 ? 6 ns minimum pulse widths 17 clk high or low pulse width write path/read 6 ? 5 ? ns 18 clock cycle frequency ? ? ? 75 mhz 19 clock cycle time ? ? 13 ? ns notes: 1. see test circuits and waveforms. t a = ? 40c to + 85c. 2. skew between any two outputs of the same package and switching in the same direction.
industrial temperature range idt74lvch16702a 3.3v cmos 18-bit read/write buffer with 5v tolerant i/o 7 open v load gnd v cc pulse generator d.u.t. 500 ? 500 ? c l r t v in v out (1, 2) lvc link input v ih 0v v oh v ol t plh1 t sk (x) output 1 output 2 t phl1 t sk (x) t plh2 t phl2 v t v t v oh v t v ol t sk (x) = t plh2 - t plh1 or t phl2 - t phl1 lvc link same phase input transition opposite phase input transition 0v 0v v oh v ol t plh t phl t phl t plh output v ih v t v t v ih v t lvc link data input 0v 0v 0v 0v t rem timing input asynchronous control synchronous control t su t h t su t h v ih v t v ih v t v ih v t v ih v t lvc link low-high-low pulse high-low-high pulse v t t w v t lvc link control input t plz 0v output normally low t pzh 0v switch closed output normally high enable disable switch open t phz 0v v lz v oh v t v t t pzl v load/2 v load/2 v ih v t v ol v hz lvc link test circuits and waveforms propagation delay test circuit for all outputs enable and disable times set-up, hold, and release times notes: 1. for t sk (o) output1 and output2 are any two outputs. 2. for t sk (b) output1 and output2 are in the same bank. definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. notes: 1. pulse generator for all pulses: rate 10mhz; t f 2.5ns; t r 2.5ns. 2. pulse generator for all pulses: rate 10mhz; t f 2ns; t r 2ns. output skew - t sk ( x ) pulse width note: 1. diagram shown for input control enable-low and input control disable-high. symbol v cc (1) = 3.3v0.3v v cc (1) = 2.7v v cc (2) = 2.5v0.2v unit v load 6 6 2 x vcc v v ih 2.7 2.7 vcc v v t 1.5 1.5 vcc / 2 v v lz 300 300 150 mv v hz 300 300 150 mv c l 50 50 30 pf test conditions switch position test switch open drain disable low v load enable low disable high gnd enable high all other tests open
industrial temperature range 8 idt74lvch16702a 3.3v cmos 18-bit read/write buffer with 5v tolerant i/o ordering information corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com idt xx lvc xxxx xx package device type temp. range pv pa pf 16 74 shrink small outline package thin shrink small outline package thin very small outline package 18-bit read/write buffer -40c to +85c xxx family bus-hold 702a bus-hold double-density, 24ma h
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